Copyright: Copyright ® 1995-1997  Virtual Micro Design


Instruction Set
 Virtual Micro Design - 68HC11 Instruction Set

License Agreement

Alphabetical instruction list

ABA	BRCLR	INX	SBA
ABX	BRN	INY	SBC
ABY	BRSET	JMP	SEC
ADC	BSET	JSR	SEI
ADD	BSR	LDA	SEV
ADDD	BVC	LDD	STA
AND	BVS	LDS	STD
ASL	CBA	LDX	STOP
ASLD	CLC	LDY	STS
ASR	CLI	LSL	STX
BCC	CLR	LSLD	STY
BCLR	CLV	LSR	SUB
BCS	CMP	LSRD	SUBD
BEQ	COM	MUL	SWI
BGE	CPD	NEG	TAB
BGT	CPX	NOP	TAP
BHI	CPY	ORA	TBA
BHS	DAA	PSH	TEST
BIT	DEC	PSHX	TPA
BLE	DES	PSHY	TST
BLO	DEX	PUL	TSX
BLS	DEY	PULX	TSY
BLT	EOR	PULY	TXS
BMI	FDIV	ROL	TYS
BNE	IDIV	ROR	WAI
BPL	INC	RTI	XGDX
BRA	INS	RTS	XGDY

Virtual Micro Design provides a complete microcontroller simulator for:

- 68HC11, 68HC705, 68HC705B5, 68HC705B16, 68HC705B32,

- PIC16C54, 55, 56, 57, PIC16C554, 556, 558

- PIC16C84, PIC16F84, PIC16C83, PIC16C71

- ST6210, 15, 20, 25,

- ST6252, 53, 60, 62, 63, 65

- 8031,51, 8032,52

Web sites: 	http://idls.izarbel.tm.fr/entp/techer

http://www.sistudio.com/umps

Copyright © 1995-1997 Virtual Micro Design, All rights reserved.


ABA
  back	ABA	Add ACCB to ACCA

Operation:	ACCA ← ACCA + ACCB

Description:	Adds the contents of accumulator B to the contents of accumulator A and places the result in accumulator A. Accumulator B is not changed. This instaruction affects the H condition code bit, so it is suitable for use in BCD arithmetic operations (see also DAA).

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	X	-	X	X	X	X
Bytes:	1

Cycles:	2

Encoding:	1B


ABX
  back	ABX	Add ACCB to Index Register X

Operation:	IX ← IX + ACCB

Description:	Adds the 8-bit unsigned contents of accumulator B to the contents of index register X (IX) considering the possible carry out of the low order byte of the index register X; places the result in index register X (IX). Accumulator B is not changed. There is no equivalent instruction to add accumulator A to an index regsiter.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	1

Cycles:	3

Encoding:	3A


ABY
  back	ABY	Add ACCB to Index Register Y

Operation:	IY ← IY + ACCB

Description:	Adds the 8-bit unsigned contents of accumulator B to the contents of index register Y (IY) considering the possible carry out of the low order byte of the index register X; places the result in index register Y (IY). Accumulator B is not changed. There is no equivalent instruction to add accumulator A to an index regsiter.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	4

Encoding:	18  3A


ADC
  back	ADC	Add with Carry

Operation:	ACCx ← (ACCx) + (M) + C

Description:	Adds the contents of the C bit to the sum of the contents of ACCX and M and place the result in ACCX. This instruction affects the H condition code bit, so it is suitable for use in BCD arithmetic operations (see also DAA).

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	X	-	X	X	X	X
Variations

ADCA #data

Bytes:	2

Cycles:	2

Encoding:	89  data

Operation:	ACCA ← ACCA + data + C

ADCA data8

Bytes:	2

Cycles:	3

Encoding:	99  data8

Operation:	ACCA ← ACCA + (data8) + C

ADCA data16

Bytes:	3

Cycles:	4

Encoding:	B9  dataHI  dataLO

Operation:	ACCA ← ACCA + (data16) + C

ADCA index,X

Bytes:	2

Cycles:	4

Encoding:	A9  index

Operation:	ACCA ← ACCA + (X+index) + C

ADCA index,Y

Bytes:	3

Cycles:	5

Encoding:	18  A9  index

Operation:	ACCA ← ACCA + (Y+index) + C

ADCB #data

Bytes:	2

Cycles:	2

Encoding:	C9  data

Operation:	ACCB ← ACCB + data + C

ADCB data8

Bytes:	2

Cycles:	3

Encoding:	D9  data8

Operation:	ACCB ← ACCB + (data8) + C

ADCB data16

Bytes:	3

Cycles:	4

Encoding:	F9  dataHI  dataLO

Operation:	ACCB ← ACCB + (data16) + C

ADCB index,X

Bytes:	2

Cycles:	4

Encoding:	E9  index

Operation:	ACCB ← ACCB + (X+index) + C

ADCB index,Y

Bytes:	3

Cycles:	5

Encoding:	18  E9  index

Operation:	ACCB ← ACCB + (Y+index) + C


ADD
  back	ADD	Add without Carry

Operation:	ACCx ← (ACCx) + (M)

Description:	Adds the contents of M to the contents of ACCX and place the result in ACCx. This instruction affects the H condition code bit, so it is suitable for use in BCD arithmetic operations (see also DAA).

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	X	-	X	X	X	X
Variations

ADDA #data

Bytes:	2

Cycles:	2

Encoding:	8B  data

Operation:	ACCA ← ACCA + data

ADDA data8

Bytes:	2

Cycles:	3

Encoding:	9B  data8

Operation:	ACCA ← ACCA + (data8)

ADDA data16

Bytes:	3

Cycles:	4

Encoding:	BB  dataHI  dataLO

Operation:	ACCA ← ACCA + (data16)

ADDA index,X

Bytes:	2

Cycles:	4

Encoding:	AB  index

Operation:	ACCA ← ACCA + (X+index)

ADDA index,Y

Bytes:	3

Cycles:	5

Encoding:	18  AB  index

Operation:	ACCA ← ACCA + (Y+index)

ADDB #data

Bytes:	2

Cycles:	2

Encoding:	CB  data

Operation:	ACCB ← ACCB + data

ADDB data8

Bytes:	2

Cycles:	3

Encoding:	DB  data8

Operation:	ACCB ← ACCB + (data8)

ADDB data16

Bytes:	3

Cycles:	4

Encoding:	FB  dataHI  dataLO

Operation:	ACCB ← ACCB + (data16)

ADDB index,X

Bytes:	2

Cycles:	4

Encoding:	EB  index

Operation:	ACCB ← ACCB + (X+index)

ADDB index,Y

Bytes:	3

Cycles:	5

Encoding:	18  EB  index

Operation:	ACCB ← ACCB + (Y+index)


ADDD
  back	ADDD	Add Double Accumulator

Operation:	ACCD ← ACCD + (M:M+1)

Description:	Adds the contents of M concatenned with M+1 to the contents of ACCD and place the result in ACCD. Accumulator A corresponds to the high-order half of the 16-bit double accumulator D.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Variations

ADDD #data16

Bytes:	3

Cycles:	4

Encoding:	C3  dataHI  dataLO

Operation:	ACCD ← ACCD + data16

ADDD data8

Bytes:	2

Cycles:	5

Encoding:	D3  data

Operation:	ACCD ← ACCD + (M:M+1)

ADDD data16

Bytes:	3

Cycles:	6

Encoding:	F3  dataHI  dataLO

Operation:	ACCD ← ACCD + (M:M+1)

ADDD index,X

Bytes:	2

Cycles:	6

Encoding:	E3  index

Operation:	ACCD ← ACCD + (X+index:X+index+1)

ADDD index,Y

Bytes:	3

Cycles:	7

Encoding:	18  E3  index

Operation:	ACCD ← ACCD + (Y+index:Y+index+1)


AND
  back	AND	Logical AND

Operation:	ACCx ← (ACCx) AND (M)

Description:	ANDs the contents of M to the contents of ACCX and place the result in ACCx. This instruction affects the H condition code bit, so it is suitable for use in BCD arithmetic operations (see also DAA).

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

ANDA #data

Bytes:	2

Cycles:	2

Encoding:	84  data

Operation:	ACCA ← ACCA  AND data

ANDA data8

Bytes:	2

Cycles:	3

Encoding:	94  data8

Operation:	ACCA ← ACCA  AND (data8)

ANDA data16

Bytes:	3

Cycles:	4

Encoding:	B4  dataHI  dataLO

Operation:	ACCA ← ACCA  AND (data16)

ANDA index,X

Bytes:	2

Cycles:	4

Encoding:	A4  index

Operation:	ACCA ← ACCA  AND (X+index)

ANDA index,Y

Bytes:	3

Cycles:	5

Encoding:	18  A4  index

Operation:	ACCA ← ACCA  AND (Y+index)

ANDB #data

Bytes:	2

Cycles:	2

Encoding:	C4  data

Operation:	ACCB ← ACCB  AND data

ANDB data8

Bytes:	2

Cycles:	3

Encoding:	D4  data8

Operation:	ACCB ← ACCB  AND (data8)

ANDB data16

Bytes:	3

Cycles:	4

Encoding:	F4  dataHI  dataLO

Operation:	ACCB ← ACCB  AND (data16)

ANDB index,X

Bytes:	2

Cycles:	4

Encoding:	E4  index

Operation:	ACCB ← ACCB  AND (X+index)

ANDB index,Y

Bytes:	3

Cycles:	5

Encoding:	18  E4  index

Operation:	ACCB ← ACCB  AND (Y+index)


ASL
  back	ASL	Arithmetic Shift Left

Operation:

Description:	Shifts all bits of the ACCx or M one place to the left. Bit 0 is loaded with a zero. The C bit in the CCR is loaded from the most significant bit of ACCx or M.

Same as LSL instruction.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Variations

ASLA    (or LSLA)

Bytes:	1

Cycles:	2

Encoding:	48

Operation:	Shift ACCA left

ASLB    (or LSLB)

Bytes:	1

Cycles:	2

Encoding:	58

Operation:	Shift ACCB left

ASL data16    (or LSL)

Bytes:	3

Cycles:	6

Encoding:	78  dataHI  dataLO

Operation:	Shift (data) left

ASL index,X    (or LSL)

Bytes:	2

Cycles:	6

Encoding:	68  data

Operation:	Shift (X+index) left

ASL index,Y    (or LSL)

Bytes:	3

Cycles:	7

Encoding:	18  68  data

Operation:	Shift (Y+index) left


ASLD
  back	ASLD	Arithmetic Shift Left Double Accumulator

Operation:

Description:	Shifts all bits of ACCD one place to the left. Bit 0 is loaded with a zero. The C bit in the CCR is loaded from the most significant bit of ACCD.

Same as LSLD instruction.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Bytes:	1

Cycles:	3

Encoding:	05


ASR
  back	ASR	Arithmetic Shift Right

Operation:

Description:	Shifts all bits of the ACCx or M one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C bit of the CCR. This operation effectively divides a twos complement value by two without changing its sign. The carry bit can be used to round the result.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Variations

ASRA

Bytes:	1

Cycles:	2

Encoding:	47

Operation:	Shift ACCA right

ASRB

Bytes:	1

Cycles:	2

Encoding:	57

Operation:	Shift ACCB right

ASR data16

Bytes:	3

Cycles:	6

Encoding:	77  dataHI  dataLO

Operation:	Shift (data) right

ASR index,X

Bytes:	2

Cycles:	6

Encoding:	67 data

Operation:	Shift (X+index) right

ASR index,Y

Bytes:	3

Cycles:	7

Encoding:	18  67  data

Operation:	Shift (Y+index) right


BCC
  back	BCC	Branch if Carry Clear

Operation:	PC ←  PC + $0002 + rel   	IF C=0

Description:	Test the state of the C bit in the CCR and causes a branch if C is clear.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	24  rel


BCLR
  back	BCLR	Clear Bit(s) in Memory

Operation:	(M) ← (M) and NOT(MASK)

Description:	Clear multiple bits in location M. The bit(s) to be cleared are specified by ones in the mask byte. All other bits in M are rewritten to their current state.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

BCLR  data  mask

Bytes:	3

Cycles:	6

Encoding:	15  data  mask

Operation:	(data) ← (data) and NOT(MASK)

BCLR  index,X  mask

Bytes:	3

Cycles:	7

Encoding:	1D  index  mask

Operation:	(X+index) ← (X+index) and NOT(MASK)

BCLR  index,Y  mask

Bytes:	4

Cycles:	8

Encoding:	18  1D  index  NOT(mask)

Operation:	(Y+index) ← (Y+index) and NOT(MASK)


BCS
  back	BCS	Branch if Carry Set

Operation:	PC ←  PC + $0002 + rel   	IF C=1

Description:	Test the state of the C bit in the CCR and causes a branch if C is set.

See BRA instruction for further details of the execution of the branch.

Comments:	Same OPCODE as BLO

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	25  rel


BEQ
  back	BEQ	Branch if Equal

Operation:	PC ← PC + $0002 + rel   	IF Z=1

Description:	Test the state of the Z bit in the CCR and causes a branch if C is set.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	27  rel


BGE
  back	BGE	Branch if Greater than or Equal to Zero

Operation:	PC ←  PC + $0002 + rel   	IF (N xor V) = 0

i.e. IF (ACCX ≥ M) 	(twos-complement signed numbers)

Description:	If the BGE instruction is executed immediately after execution of any of the instructions CBA, CMP(A,B or D), CP(X or Y), SBA, SUB(A,B or D), the branch will occur if and only if the twos-complement number represented by the ACCx was greater than or equal to the two-complement number represented by M.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	2C  rel


BGT
  back	BGT	Branch if Greater than Zero

Operation:	PC ← PC + $0002 + rel   	IF (N xor V) or Z  = 0

i.e. IF (ACCX > M) 	(twos-complement signed numbers)

Description:	If the BGT instruction is executed immediately after execution of any of the instructions CBA, CMP(A,B or D), CP(X or Y), SBA, SUB(A,B or D), the branch will occur if and only if the twos-complement number represented by the ACCx was greater than the two-complement number represented by M.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	2C  rel


BHI
  back	BHI	Branch if Higher

Operation:	PC ← PC + $0002 + rel   IF (C or Z)  = 0

i.e. IF (ACCX > M)	(unsigned binary numbers)

Description:	If the BHI instruction is executed immediately after execution of any of the instructions CBA, CMP(A,B or D), CP(X or Y), SBA, SUB(A,B or D), the branch will occur if and only if the unsigned binary number represented by the ACCx was greater than the unsigned binary number represented by M. Generally not useful after INC/DEC, LD/ST, TST/CLR/COM because the instructions do not affect the C bit in the CCR.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	22  rel


BHS
  back	BHS	Branch if Higher or Same

Operation:	PC ← PC + $0002 + rel   IF C = 0

i.e. IF (ACCX ≥ M)	(unsigned binary numbers)

Description:	If the BHS instruction is executed immediately after execution of any of the instructions CBA, CMP(A,B or D), CP(X or Y), SBA, SUB(A,B or D), the branch will occur if and only if the unsigned binary number represented by the ACCx was greater than or equal to the unsigned binary number represented by M. Generally not useful after INC/DEC, LD/ST, TST/CLR/COM because the instructions do not affect the C bit in the CCR.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	24  rel


BIT
  back	BIT	Bit Test

Operation:	 (ACCx) AND (M)

Description:	Performs the logical AND operation between the contents of ACCX to the contents of M and modifies the condition codes accordingly. Neither the contents of ACCX or M operands are affected. (Each bit of the result of the AND would be the logical AND of the corresponding bits of ACCX and M).

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

BITA #data

Bytes:	2

Cycles:	2

Encoding:	85  data

Operation:	ACCA  AND data

BITA data8

Bytes:	2

Cycles:	3

Encoding:	95  data8

Operation:	ACCA  AND (data8)

BITA data16

Bytes:	3

Cycles:	4

Encoding:	B5  dataHI  dataLO

Operation:	ACCA  AND (data16)

BITA index,X

Bytes:	2

Cycles:	4

Encoding:	A5  index

Operation:	ACCA  AND (X+index)

BITA index,Y

Bytes:	3

Cycles:	5

Encoding:	18  A5  index

Operation:	ACCA  AND (Y+index)

BITB #data

Bytes:	2

Cycles:	2

Encoding:	C5  data

Operation:	ACCB  AND data

BITB data8

Bytes:	2

Cycles:	3

Encoding:	D5  data8

Operation:	ACCB  AND (data8)

BITB data16

Bytes:	3

Cycles:	4

Encoding:	F5  dataHI  dataLO

Operation:	ACCB  AND (data16)

BITB index,X

Bytes:	2

Cycles:	4

Encoding:	E5  index

Operation:	ACCB  AND (X+index)

BITB index,Y

Bytes:	3

Cycles:	5

Encoding:	18  E5  index

Operation:	ACCB  AND (Y+index)


BLE
  back	BLE	Branch if Less than or Equal to Zero

Operation:	PC ← PC + $0002 + rel   	IF (Z or (N xor V)) = 1

i.e. IF (ACCX ≤ M)	(twos-complement signed numbers)

Description:	If the BLE instruction is executed immediately after execution of any of the instructions CBA, CMP(A,B or D), CP(X or Y), SBA, SUB(A,B or D), the branch will occur if and only if the twos-complement number represented by the ACCx was less than or equal to the twos-complement number represented by M.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	2F  rel


BLO
  back	BLO	Branch if Lower

Operation:	PC ← PC + $0002 + rel   	IF C = 1

i.e. IF (ACCX < M)	(twos-complement signed numbers)

Description:	If the BLO instruction is executed immediately after execution of any of the instructions CBA, CMP(A,B or D), CP(X or Y), SBA, SUB(A,B or D), the branch will occur if and only if the twos-complement number represented by the ACCx was less than the twos-complement number represented by M. Generally not useful after INC/DEC, LD/ST, TST/CLR/COM because the instructions do not affect the C bit in the CCR.

See BRA instruction for further details of the execution of the branch.

Comments:	Same OPCODE as BCS

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	25  rel


BLS
  back	BLS	Branch if Lower or Same

Operation:	PC ← PC + $0002 + rel   	IF (C or Z) = 1

i.e. IF (ACCX ≤ M)	(twos-complement signed numbers)

Description:	If the BLO instruction is executed immediately after execution of any of the instructions CBA, CMP(A,B or D), CP(X or Y), SBA, SUB(A,B or D), the branch will occur if and only if the twos-complement number represented by the ACCx was less than or equal to the twos-complement number represented by M. Generally not useful after INC/DEC, LD/ST, TST/CLR/COM because the instructions do not affect the C bit in the CCR.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	23  rel


BLT
  back	BLT	Branch if Less than Zero

Operation:	PC ← PC + $0002 + rel   	IF (N xor V) = 1

i.e. IF (ACCX < M)	(twos-complement signed numbers)

Description:	If the BLT instruction is executed immediately after execution of any of the instructions CBA, CMP(A,B or D), CP(X or Y), SBA, SUB(A,B or D), the branch will occur if and only if the twos-complement number represented by the ACCx was less than the twos-complement number represented by M.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	2D  rel


BMI
  back	BMI	Branch if Minus

Operation:	PC ← PC + $0002 + rel   	IF N = 1

Description:	Test the state of the N bit in the CCR and causes a branch if N is set.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	2B  rel


BNE
  back	BNE	Branch if Not Equal to Zero

Operation:	PC ← PC + $0002 + rel   	IF Z = 0

Description:	Test the state of the Z bit in the CCR and causes a branch if Z is clear.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	26  rel


BPL
  back	BPL	Branch if Plus

Operation:	PC ← PC + $0002 + rel   	IF N = 0

Description:	Test the state of the N bit in the CCR and causes a branch if N is clear.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	2A  rel


BRA
  back	BRA	Branch Always

Operation:	PC ← PC + $0002 + rel

Description:	Unconditionnal branch to the address given by the foregoing formula, in which Rel is the relative offset stored as a twos complement number in the second byte of machine code corresponding to the branch instruction.

The source program specifies the destination of any branch instruction by its absolute address, either as a numerical value or as a symbol or expression, that can be numerically evaluated by the assembler. The assembler obtains the relative address, Rel, from the absolute address and the current value of the location counter.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	20  rel


BRCLR
  back	BRCLR	Branch if Bit(s) Clear

Operation:	PC ← PC + $0004(/5) + rel	IF  (M and MASK) = 0

Description:	Performs the logical AND of location M and the mask supplied with the instruction, then branches if the result is zero (only if all bits corresponding to ones in the mask byte are zeros in the tested byte).

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Variations

BRCLR  data  mask rel

Bytes:	4

Cycles:	6

Encoding:	13  data  mask  rel

Operation:	PC ← PC + $0004 + rel	IF  ((data) and MASK) = 0

BRCLR  index,X  mask  rel

Bytes:	4

Cycles:	7

Encoding:	1F  index  mask  rel

Operation:	PC ← PC + $0004 + rel	IF  ((X+index) and MASK) = 0

BRCLR  index,Y  mask  rel

Bytes:	5

Cycles:	8

Encoding:	18  1F  index  mask  rel

Operation:	PC ← PC + $0005 + rel	IF  ((X+index) and MASK) = 0


BRN
  back	BRN	Branch Never

Operation:	PC ← PC + $0002

Description:	Never branches. In effect, this instruction can be considered as a two-byte NOP requiring three cycles for execution. Its inclusion in the instruction set is to provide a complement for the BRA instruction. The instruction is useful during program debug to negate the effect of another branch instruction without disturbing the offset byte. Having a complement for BRA is also useful in compiler implementations.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	21  rel


BRSET
  back	BRSET	Branch if Bit(s) Set

Operation:	PC ← PC + $0004(/5) + rel	IF  (not(M) and MASK) = 0

Description:	Performs the logical AND of location M inverted and the mask supplied with the instruction, then branches if the result is zero (only if all bits corresponding to ones in the mask byte are ones in the tested byte).

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Variations

BRSET  data  mask rel

Bytes:	4

Cycles:	6

Encoding:	12  data  mask  rel

Operation:	PC ←  PC + $0004 + rel	IF  (not(data) and MASK) = 0

BRSET  index,X  mask  rel

Bytes:	4

Cycles:	7

Encoding:	1E  index  mask  rel

Operation:	PC ← PC + $0004 + rel	IF  (not(X+index) and MASK) = 0

BRSET  index,Y  mask  rel

Bytes:	5

Cycles:	8

Encoding:	18  1E  index  mask  rel

Operation:	PC ← PC + $0005 + rel	IF  (not(Y+index) and MASK) = 0


BSET
  back	BSET	Set Bit(s) in Memory

Operation:	(M) ← (M) or MASK

Description:	Set multiple bits in location M. The bit(s) to be set are specified by ones in the mask byte. All other bits in M are unaffected.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

BSET  data  mask

Bytes:	3

Cycles:	6

Encoding:	14  data  mask

Operation:	(data) ← (data) or MASK

BSET  index,X  mask

Bytes:	3

Cycles:	7

Encoding:	1C  index  mask

Operation:	(X+index) ← (X+index) or MASK

BSET  index,Y  mask

Bytes:	4

Cycles:	8

Encoding:	18  1C  index  mask

Operation:	(Y+index) ← (Y+index) or MASK


BSR
  back	BSR	Branch to Subroutine

Operation:	PC ←  PC + $0002

(SP) ←  PCL,   SP ←  SP - $0001

(SP) ←  PCH,   SP ←  SP - $0001

PC ←  PC + rel

Description:	The program counter is incremented by two (this will be the return address). The least significant byte of the contents of the program counter (low-order return address) is pushed onto the stack. The stack pointer is then decremented by one. The most significant byte of the contents of the program counter (high-order return address) is pushed onto the stack. The stack pointer is then decremented by one. A branch then occurs to the location specified by the branch offset.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	6

Encoding:	8D  rel


BVC
  back	BVC	Branch if Overflow Clear

Operation:	PC ← PC + $0002 + rel   	IF V = 0

Description:	Test the state of the V bit in the CCR and causes a branch if V is clear.

Used after an operation on twos-complements binaries values, this instruction will cause a branch if there was NO overflow. That is, branch if the twos-complements result was valid.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	28  rel


BVS
  back	BVS	Branch if Overflow Set

Operation:	PC ← PC + $0002 + rel   	IF V = 1

Description:	Test the state of the V bit in the CCR and causes a branch if V is set.

Used after an operation on twos-complements binaries values, this instruction will cause a branch if there was an overflow. That is, branch if the twos-complements result was invalid.

See BRA instruction for further details of the execution of the branch.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	3

Encoding:	29  rel


CBA
  back	CBA	Compare Accumulators

Operation:	ACCA  -  ACCB

Description:	Compare the contents of ACCA to the contents of ACCB and set the condition codes, which may be used for arithmetic and logical conditionnal branches. Both operands are unaffected.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Bytes:	1

Cycles:	2

Encoding:	11


CLC
  back	CLC	Clear Carry

Operation:	C ←  0

Description:	Clears the C bit in the CCR.

CLC may be used to set up the C bit prior to a shift or rotate instruction involving the C bit.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	0
Bytes:	1

Cycles:	2

Encoding:	0C


CLI
  back	CLI	Clear Interrupt Mask

Operation:	I ←  0

Description:	Clears the Interrupt mask bit in the CCR. When the I bit is clear, interrupts are enabled. There is a one E-Clock cycle delay in the clearing mechanism for the I bit so that, if interrupts where previously disabled, the next instruction after a CLI will always be executed, even if there was an interrupt pending prior to execution of the CLI instruction.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	0
Bytes:	1

Cycles:	2

Encoding:	0E


CLR
  back	CLR	Clear

Operation:	ACCx ←  0

Description:	The contents of ACCX or M are replaced with zeros.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	0	1	0	0
Bytes:	1

Cycles:	2

Encoding:	0E

Variations

CLRA

Bytes:	1

Cycles:	2

Encoding:	4F

Operation:	ACCA ← 0

CLRB

Bytes:	1

Cycles:	2

Encoding:	5F

Operation:	ACCB ← 0

CLR  data16

Bytes:	3

Cycles:	6

Encoding:	7F  dataHI  dataLO

Operation:	(data16) ← 0

CLR  index,X

Bytes:	2

Cycles:	6

Encoding:	6F  index

Operation:	 (X+index) ← 0

CLR  index,Y

Bytes:	2

Cycles:	6

Encoding:	18  6F  index

Operation:	 (Y+index) ← 0


CLV
  back	CLV	Clear Twos-Complement Overflow bit

Operation:	V ←  0

Description:	Clears the twos complement overflow bit in the CCR.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	0	-
Bytes:	1

Cycles:	2

Encoding:	0A


CMP
  back	CMP	Compare

Operation:	 (ACCx) - (M)

Description:	Compare the contents of ACCx to the contents of M and sets the condition codes, which may be used for arithmetic and logical conditionnal branching. Both operands are unaffected.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Variations

CMPA #data

Bytes:	2

Cycles:	2

Encoding:	81  data

Operation:	ACCA - data

CMPA data8

Bytes:	2

Cycles:	3

Encoding:	91  data8

Operation:	ACCA - (data8)

CMPA data16

Bytes:	3

Cycles:	4

Encoding:	B1  dataHI  dataLO

Operation:	ACCA - (data16)

CMPA index,X

Bytes:	2

Cycles:	4

Encoding:	A1  index

Operation:	ACCA - (X+index)

CMPA index,Y

Bytes:	3

Cycles:	5

Encoding:	18  A1  index

Operation:	ACCA - (Y+index)

CMPB #data

Bytes:	2

Cycles:	2

Encoding:	C1  data

Operation:	ACCB - data

CMPB data8

Bytes:	2

Cycles:	3

Encoding:	D1  data8

Operation:	ACCB - (data8)

CMPB data16

Bytes:	3

Cycles:	4

Encoding:	F1  dataHI  dataLO

Operation:	ACCB - (data16)

CMPB index,X

Bytes:	2

Cycles:	4

Encoding:	E1  index

Operation:	ACCB - (X+index)

CMPB index,Y

Bytes:	3

Cycles:	5

Encoding:	18  E1  index

Operation:	ACCB - (Y+index)


COM
  back	COM	Complement

Operation:	ACCx ←  $FF - ACCx

or (M) ←  $FF - (M)

Description:	Replace the contents of ACCX or M with its ones complement. (Each bit of the contents of ACCX or M is replaced with the complement of that bit). To complement a value without affecting the C bit, Exclusive OR the value with $FF.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	1
Variations

COMA

Bytes:	1

Cycles:	2

Encoding:	43

Operation:	ACCA ← $FF - ACCA

COMB

Bytes:	1

Cycles:	2

Encoding:	53

Operation:	ACCB ← $FF - ACCB

COM data16

Bytes:	4

Cycles:	6

Encoding:	1F  dataHI  dataLO

Operation:	(data16) ←  $FF - (data16)

COM  index,X

Bytes:	2

Cycles:	6

Encoding:	63  index

Operation:	(X+index) ← $FF - (X+index)

COM  index,Y

Bytes:	2

Cycles:	6

Encoding:	18  63  index

Operation:	(Y+index) ← $FF - (Y+index)


CPD
  back	CPD	Compare Double Accumulator

Operation:	 (ACCD) - (M:M+1)

Description:	Compare the contents of the accumulator D with a 16-bit value at the address specified and sets the condition codes accordingly. The compare is accomplished internally by doing a 16-bit subtract of (M:M+1) from accumulator D without modifying either accumulator D or (M:M+1).

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Variations

CPD #data

Bytes:	4

Cycles:	4

Encoding:	1A  83  dataHI  dataLO

Operation:	ACCD - data

CPD data8

Bytes:	3

Cycles:	6

Encoding:	1A  93  data8

Operation:	ACCD - (data8)

CPD data16

Bytes:	4

Cycles:	7

Encoding:	1A  B3  dataHI  dataLO

Operation:	ACCD - (data16)

CPD index,X

Bytes:	3

Cycles:	7

Encoding:	1A  A3  index

Operation:	ACCD - (X+index)

CPD index,Y

Bytes:	3

Cycles:	7

Encoding:	CD  A3  index

Operation:	ACCA - (Y+index)


CPX
  back	CPX	Compare Index Register X

Operation:	 (IX) - (M:M+1)

Description:	Compare the contents of the index register X with a 16-bit value at the address specified and sets the condition codes accordingly. The compare is accomplished internally by doing a 16-bit subtract of (M:M+1) from index register X without modifying either index register X or (M:M+1).

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Variations

CPX #data

Bytes:	3

Cycles:	4

Encoding:	8C  dataHI  dataLO

Operation:	X - data

CPX data8

Bytes:	2

Cycles:	5

Encoding:	9C  data8

Operation:	X - (data8)

CPX data16

Bytes:	3

Cycles:	6

Encoding:	BC  dataHI  dataLO

Operation:	X - (data16)

CPX index,X

Bytes:	2

Cycles:	6

Encoding:	AC  index

Operation:	X - (X+index)

CPX index,Y

Bytes:	3

Cycles:	7

Encoding:	CD  AC  index

Operation:	X - (Y+index)


CPY
  back	CPY	Compare Index Register Y

Operation:	 (IY) - (M:M+1)

Description:	Compare the contents of the index register Y with a 16-bit value at the address specified and sets the condition codes accordingly. The compare is accomplished internally by doing a 16-bit subtract of (M:M+1) from index register Y without modifying either index register Y or (M:M+1).

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Variations

CPY #data

Bytes:	4

Cycles:	5

Encoding:	18  8C  dataHI  dataLO

Operation:	Y - data

CPY data8

Bytes:	3

Cycles:	6

Encoding:	18  9C  data8

Operation:	Y - (data8)

CPY data16

Bytes:	4

Cycles:	7

Encoding:	18  BC  dataHI  dataLO

Operation:	Y - (data16)

CPY index,X

Bytes:	3

Cycles:	6

Encoding:	1A  AC  index

Operation:	Y - (X+index)

CPY index,Y

Bytes:	3

Cycles:	7

Encoding:	18  AC  index

Operation:	Y - (Y+index)


DAA
  back	DAA	Decimal Adjust ACCA

Operation:	The following table summarizes the operation of the DAA instruction for all legal combinations of input operands. A correction factor (column 5 in the following table) is added to ACCA to restore the result of an addition of two BCD operands to a valid BCD value and set or clear the carry bit.

State of C bit before DAA  1	Upper Half-Byte of ACCA 2	Initial Half-Carry H bit 3	Lower Half-Byte of ACCA 4	Number added to ACCA by DAA	State of C bit after DAA 6
0	0-9	0	0-9	00	0
0	0-8	0	A-F	06	0
0	0-9	1	0-3	06	0
0	A-F	0	0-9	60	1
0	9-F	0	A-F	66	1
0	A-F	1	0-3	66	1
1	0-2	0	0-9	60	1
1	0-3	0	A-F	66	1
1	0-3	1	0-3	66	1

Columns1 through 4 of the above table represent all possible cases wich can result from any of the operations ABA, ADD, or ADC, with initial carry either set or clear, applied to two binaries-coded-decimal operands. The table showns hexadecimal values.

Description:	If the contents of ACCA and the state of the carry/borrow bit C and the state of the half-carry bit H are all the result of applying any of the operations ABA, ADD or ADC to binary-coded-decimal operands, with or without an initial carry, the DAA operation will adjust the contents of ACCA and the carry bit C in the CCR to represent the correct binary-coded-decimal sum and the correct state of the C bit.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	?	X

Bytes:	1

Cycles:	2

Encoding:	19


DEC
  back	DEC	Decrement

Operation:	 (ACCx) ← (ACCx) - 1

or (M) ← (M) - 1

Description:	Subtract one from the contents of ACCx or M.

The N,Z, and V bits in the CCR are set or cleared according to the results of the operation. The C bit in the CCR is not affected by the operation, thus allowing the DEC instruction to be used as a loop counter in multiple precision computations.

When operating on unsigned values, only BEQ and BNE branches can be expected to perform consistently. When operating on twos-complement values, all signed branches are available.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	-
Variations

DECA

Bytes:	1

Cycles:	2

Encoding:	4A

Operation:	ACCA ← ACCA - 1

DECB

Bytes:	1

Cycles:	2

Encoding:	5A

Operation:	ACCB ← ACCB - 1

DEC data16

Bytes:	3

Cycles:	6

Encoding:	7A  dataHI  dataLO

Operation:	(data16) ← (data16) - 1

DEC index,X

Bytes:	2

Cycles:	6

Encoding:	6A  index

Operation:	(X+index) ← (X+index) - 1

DEC index,Y

Bytes:	3

Cycles:	7

Encoding:	18  6A  index

Operation:	(Y+index) ← (Y+index) - 1


DES
  back	DES	Decrement Stack Pointer

Operation:	SP ← SP - $0001

Description:	Subtract one from the stack pointer.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	1

Cycles:	2

Encoding:	34


DEX
  back	DEX	Decrement Index Register X

Operation:	IX ← IX - $0001

Description:	Subtract one from the index register X.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	X	-	-
Bytes:	1

Cycles:	3

Encoding:	09


DEY
  back	DEY	Decrement Index Register Y

Operation:	IY ← IY - $0001

Description:	Subtract one from the index register Y.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	X	-	-
Bytes:	2

Cycles:	4

Encoding:	18  09


EOR
  back	EOR	Exclusive-OR

Operation:	ACCx ← (ACCx) XOR (M)

Description:	Performs the logical eXclusive-OR between the contents of ACCX and the contents of M and places the result in ACCx. (each bit of ACCX after the operation will be the logical exclusive-OR of the corresponding bits of M and ACCX before the operation).

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

EORA #data

Bytes:	2

Cycles:	2

Encoding:	88  data

Operation:	ACCA ← ACCA  XOR data

EORA data8

Bytes:	2

Cycles:	3

Encoding:	98  data8

Operation:	ACCA ← ACCA  XOR (data8)

EORA data16

Bytes:	3

Cycles:	4

Encoding:	B8  dataHI  dataLO

Operation:	ACCA ← ACCA  XOR (data16)

EORA index,X

Bytes:	2

Cycles:	4

Encoding:	A8  index

Operation:	ACCA ← ACCA  XOR (X+index)

EORA index,Y

Bytes:	3

Cycles:	5

Encoding:	18  A8  index

Operation:	ACCA ← ACCA  XOR (Y+index)

EORB #data

Bytes:	2

Cycles:	2

Encoding:	C8  data

Operation:	ACCB ← ACCB  XOR data

EORB data8

Bytes:	2

Cycles:	3

Encoding:	D8  data8

Operation:	ACCB ← ACCB  XOR (data8)

EORB data16

Bytes:	3

Cycles:	4

Encoding:	F8  dataHI  dataLO

Operation:	ACCB ← ACCB  XOR (data16)

EORB index,X

Bytes:	2

Cycles:	4

Encoding:	E8  index

Operation:	ACCB ← ACCB  XOR (X+index)

EORB index,Y

Bytes:	3

Cycles:	5

Encoding:	18  E8  index

Operation:	ACCB ← ACCB  XOR (Y+index)


FDIV
  back	FDIV	Fractional Divide

Operation:	ACCD / IX;  IX ← Quotient,  ACCD ← Remainder

Description:	Performs an unsigned fractionnal divide of the 16-bit numerator in the D-accumulator by the 16-bit denominator in the index register X and sets the condition codes accordingly. The quotient is placed in the index register X, and the remainder is placed in the D accumulator. The radix point is assumed to be in the same place for both the numerator and the denominator. The radix point is to the left bit 15 for the quotient. The numerator is assumed to be less than the denominator. In the case of overflow (denominator is less than or equal to the numerator) or divide by zero, the quotient is set to $FFFF, and the remainder is indeterminate.

FDIV is equivalent to multiplying the numerator by 216 and then performing a 32 X 16-bit integer divide. The result is interpreted as a binary-weighted fraction, wich resulted from the division of a 16-bit integer by a larger 16-bit integer. A result of $0001 corresponds to 0.000015, and $FFFF corresponds to 0.99998. The remainder of an IDIV instruction can be resolved into binary-weighted fraction by an FDIV instruction. The remainder of an FDIV instruction can be resolved into the next 16-bits of binary-weighted fraction by another FDIV instruction.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	X	X	X
Bytes:	1

Cycles:	3 - 41

Encoding:	03


IDIV
  back	IDIV	Integer Divide

Operation:	ACCD / IX;  IX ← Quotient,  ACCD ← Remainder

Description:	Performs an unsigned integer divide of the 16-bit numerator in the D-accumulator by the 16-bit denominator in the index register X and sets the condition codes accordingly. The quotient is placed in the index register X, and the remainder is placed in the D accumulator. The radix point is assumed to be in the same place for both the numerator and the denominator. The radix point is to the right of bit 0 for the quotient. In the case of divide by zero, the quotient is set to $FFFF, and the remainder is indeterminate.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	X	0	X
Bytes:	1

Cycles:	3 - 41

Encoding:	02


INC
  back	INC	Increment

Operation:	 (ACCx) ← (ACCx) + 1

or (M) ← (M) + 1

Description:	Add one to the contents of ACCx or M.

The N,Z, and V bits in the CCR are set or cleared according to the results of the operation. The C bit in the CCR is not affected by the operation, thus allowing the INC instruction to be used as a loop counter in multiple precision computations.

When operating on unsigned values, only BEQ and BNE branches can be expected to perform consistently. When operating on twos-complement values, all signed branches are available.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	-
Variations

INCA

Bytes:	1

Cycles:	2

Encoding:	4C

Operation:	ACCA ← ACCA + 1

INCB

Bytes:	1

Cycles:	2

Encoding:	5C

Operation:	ACCB ← ACCB + 1

INC data16

Bytes:	3

Cycles:	6

Encoding:	7C  dataHI  dataLO

Operation:	(data16) ← (data16) + 1

INC index,X

Bytes:	2

Cycles:	6

Encoding:	6C  index

Operation:	(X+index) ← (X+index) + 1

INC index,Y

Bytes:	3

Cycles:	7

Encoding:	18  6C  index

Operation:	(Y+index) ← (Y+index) + 1


INS
  back	INS	Increment Stack Pointer

Operation:	SP ← SP + $0001

Description:	Add one to the stack pointer.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	1

Cycles:	2

Encoding:	31


INX
  back	INX	Increment Index Register X

Operation:	IX ← IX + $0001

Description:	Add one to the index register X.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	X	-	-
Bytes:	1

Cycles:	3

Encoding:	08


INY
  back	INY	Increment Index Register Y

Operation:	IY ← IY + $0001

Description:	Add one to the index register Y.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	X	-	-
Bytes:	2

Cycles:	4

Encoding:	18  08


JMP
  back	JMP	Jump

Operation:	PC ← Effective address

Description:	A jump occurs to the instruction stored at the effective address. The effective address is obtain according to the rules for EXTended or INDexed addressing.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Variations

JMP data16

Bytes:	3

Cycles:	3

Encoding:	7E  dataHI  dataLO

Operation:	PC ← data16

JMP index,X

Bytes:	2

Cycles:	3

Encoding:	6E  index

Operation:	PC ← (X+index)

JMP index,Y

Bytes:	3

Cycles:	4

Encoding:	18  6E  index

Operation:	PC ← (Y+index)


JSR
  back	JSR	Jump to Subroutine

Operation:	PC ←  PC + $0002

(SP) ←  PCL,   SP   SP - $0001

(SP) ←  PCH,   SP   SP - $0001

PC ← Effective address

Description:	The program counter is incremented by three or by two, depending on the addressing mode, and the pushed onto the stack, eight bits at a time, least significant byte first. The stack pointer points to the next empty location in the stack. A jump occurs to the instruction stored at the effective address. The effective address is obtained according to the rules for EXTended, DIRect or INDexed addressing.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Variations

JSR data8

Bytes:	2

Cycles:	5

Encoding:	9D  data

JSR data16

Bytes:	3

Cycles:	6

Encoding:	BD  dataHI  dataLO

JSR index,X

Bytes:	2

Cycles:	6

Encoding:	AD  index

JSR index,Y

Bytes:	3

Cycles:	7

Encoding:	18  AD  index


LDA
  back	LDA	Load Accumulator

Operation:	AccX ←  (M)

Description:	Load the contents of memory into the 8-bit accumulator. The condition codes are set according to the data.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

LDAA #data

Bytes:	2

Cycles:	2

Encoding:	86  data

Operation:	ACCA ← data

LDAA data8

Bytes:	2

Cycles:	3

Encoding:	96  data8

Operation:	ACCA ← (data8)

LDAA data16

Bytes:	3

Cycles:	4

Encoding:	B6  dataHI  dataLO

Operation:	ACCA ← (data16)

LDAA index,X

Bytes:	2

Cycles:	4

Encoding:	A6  index

Operation:	ACCA ← (X+ index)

LDAA index,Y

Bytes:	3

Cycles:	5

Encoding:	18  A6  index

Operation:	ACCA ← (Y+ index)

LDAB #data

Bytes:	2

Cycles:	2

Encoding:	C6  data

Operation:	ACCB ← data

LDAB data8

Bytes:	2

Cycles:	3

Encoding:	D6  data8

Operation:	ACCB ← (data8)

LDAB data16

Bytes:	3

Cycles:	4

Encoding:	F6  dataHI  dataLO

Operation:	ACCB ← (data16)

LDAB index,X

Bytes:	2

Cycles:	4

Encoding:	E6  index

Operation:	ACCB ← (X+ index)

LDAB index,Y

Bytes:	3

Cycles:	5

Encoding:	18  E6  index

Operation:	ACCB ← (Y+ index)


LDD
  back	LDD	Load Double Accumulator

Operation:	ACCD ← (M:M+1)

Description:	Load the contents of memory locations M and M+1 into the double accumulator D. The condition codes are set according to the data. The information from location M is loaded into accumulator A, and the information from location M+1 is loaded into the accumulator B.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

LDD #data16

Bytes:	3

Cycles:	3

Encoding:	CC  dataHI  dataLO

Operation:	ACCD ← data16

LDD data8

Bytes:	2

Cycles:	4

Encoding:	DC  data

Operation:	ACCD ← (data8)

LDD data16

Bytes:	3

Cycles:	5

Encoding:	FC  dataHI  dataLO

Operation:	ACCD ← (data16)

LDD index,X

Bytes:	2

Cycles:	5

Encoding:	EC  index

Operation:	ACCD ← (X+index:X+index+1)

LDD index,Y

Bytes:	3

Cycles:	6

Encoding:	18  EC  index

Operation:	ACCD ← (Y+index:Y+index+1)


LDS
  back	LDS	Load Stack Pointer

Operation:	SPH ← (M)

SPL ← (M+1)

Description:	Load the most significant byte of the stack pointer from the byte of memory at the address specified by the program, and loads the least significant byte of the stack pointer from the next byte of memory at one plus the address specified by the program.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

LDS #data16

Bytes:	3

Cycles:	3

Encoding:	8E  dataHI  dataLO

Operation:	SP ← data16

LDS data8

Bytes:	2

Cycles:	4

Encoding:	9E  data

Operation:	SP ← (data8)

LDS data16

Bytes:	3

Cycles:	5

Encoding:	BE  dataHI  dataLO

Operation:	SP ← (data16)

LDS index,X

Bytes:	2

Cycles:	5

Encoding:	AE  index

Operation:	SP ← (X+index:X+index+1)

LDS index,Y

Bytes:	3

Cycles:	6

Encoding:	18  AE  index

Operation:	SP ← (Y+index:Y+index+1)


LDX
  back	LDX	Load Index Register X

Operation:	IXH ← (M)

IXL ← (M+1)

Description:	Load the most significant byte of index register X from the byte of memory at the address specified by the program, and loads the least significant byte of index register X from the next byte of memory at one plus the address specified by the program.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

LDX #data16

Bytes:	3

Cycles:	3

Encoding:	CE  dataHI  dataLO

Operation:	X ← data16

LDX data8

Bytes:	2

Cycles:	4

Encoding:	DE  data

Operation:	X ← (data8)

LDX data16

Bytes:	3

Cycles:	5

Encoding:	FE  dataHI  dataLO

Operation:	X ← (data16)

LDX index,X

Bytes:	2

Cycles:	5

Encoding:	EE  index

Operation:	X ← (X+index:X+index+1)

LDX index,Y

Bytes:	3

Cycles:	6

Encoding:	CD  EE  index

Operation:	X ← (Y+index:Y+index+1)


LDY
  back	LDY	Load Index Register Y

Operation:	IYH ← (M)

IYL ← (M+1)

Description:	Load the most significant byte of index register Y from the byte of memory at the address specified by the program, and loads the least significant byte of index register Y from the next byte of memory at one plus the address specified by the program.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

LDY #data16

Bytes:	4

Cycles:	4

Encoding:	18  CE  dataHI  dataLO

Operation:	Y ← data16

LDY data8

Bytes:	3

Cycles:	5

Encoding:	18  DE  data

Operation:	Y ← (data8)

LDY data16

Bytes:	4

Cycles:	6

Encoding:	18  FE  dataHI  dataLO

Operation:	Y ← (data16)

LDY index,X

Bytes:	3

Cycles:	6

Encoding:	1A  EE  index

Operation:	Y ← (X+index:X+index+1)

LDY index,Y

Bytes:	3

Cycles:	6

Encoding:	18  EE  index

Operation:	Y ← (Y+index:Y+index+1)


LSL
  back	LSL	Logical Shift Left

Operation:

Description:	Shifts all bits of the ACCx or M one place to the left. Bit 0 is loaded with a zero. The C bit in the CCR is loaded from the most significant bit of ACCx or M.

Same as ASL instruction.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Variations

LSLA    (or ASLA)

Bytes:	1

Cycles:	2

Encoding:	48

Operation:	Shift ACCA left

LSLB    (or ASLB)

Bytes:	1

Cycles:	2

Encoding:	58

Operation:	Shift ACCB left

LSL data16    (or ASL)

Bytes:	3

Cycles:	6

Encoding:	78  dataHI  dataLO

Operation:	Shift (data) left

LSL index,X    (or ASL)

Bytes:	2

Cycles:	6

Encoding:	68  data

Operation:	Shift (X+index) left

LSL index,Y    (or ASL)

Bytes:	3

Cycles:	7

Encoding:	18  68  data

Operation:	Shift (Y+index) left


LSLD
  back	LSLD	Arithmetic Shift Left Double Accumulator

Operation:

Description:	Shifts all bits of ACCD one place to the left. Bit 0 is loaded with a zero. The C bit in the CCR is loaded from the most significant bit of ACCD.

Same as ASLD instruction.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Bytes:	1

Cycles:	3

Encoding:	05


LSR
  back	LSR	Logical Shift Right

Operation:

Description:	Shifts all bits of ACCx or M one place to the right. Bit 7 is loaded with 0. The C bit is loaded from the least significant bit of ACCx or M.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	0	X	X	X
Variations

LSRA

Bytes:	1

Cycles:	2

Encoding:	44

Operation:	Logical Shift ACCA right

LSRB

Bytes:	1

Cycles:	2

Encoding:	54

Operation:	Logical Shift ACCB right

LSR data16

Bytes:	3

Cycles:	6

Encoding:	74  dataHI  dataLO

Operation:	Logical Shift (data) right

LSR index,X

Bytes:	2

Cycles:	6

Encoding:	64 data

Operation:	Logical Shift (X+index) right

LSR index,Y

Bytes:	3

Cycles:	7

Encoding:	18  64  data

Operation:	Logical Shift (Y+index) right


LSRD
  back	LSRD	Logical Shift Right Double Accumulator

Operation:

Description:	Shifts all bits of ACCD one place to the right. Bit 15 (MSB of ACCA) is loaded with zero. The C bit is loaded from the least significant bit of ACCD (LSB of ACCB).

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	0	X	X	X
Bytes:	1

Cycles:	3

Encoding:	04


MUL
  back	MUL	Multiply Unsigned

Operation:	ACCD ← ACCA * ACCB

Description:	Multiplies the 8-bit unsigned binary value in accumulator A by the 8-bit unsigned binary value in accumulator B to obtain a 16-bit unsigned result in the double accumulator D. Unsigned multiply allows multiple-precision operations. The carry flag allows rounding the most significant byte of the result through the sequence: MUL, ADCA #0.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	X

C: is set if bit 7 of the result (ACCB bit 7) is set; cleared otherwise.

Bytes:	1

Cycles:	3 to 10

Encoding:	3D


NEG
  back	NEG	Negate

Operation:	ACCX ← $00 − ACCX

Description:	Replaces the contents of ACCX or M with its twos complement; the value $80 is left unchanged.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Variations

NEGA

Bytes:	1

Cycles:	2

Encoding:	40

Operation:	ACCA ← $00 − ACCA

NEGB

Bytes:	1

Cycles:	2

Encoding:	50

Operation:	ACCB ← $00 − ACCB

NEG data16

Bytes:	3

Cycles:	6

Encoding:	74  dataHI  dataLO

Operation:	(data16) ← $00 − (data16)

NEG index,X

Bytes:	2

Cycles:	6

Encoding:	60 data

Operation:	(X + index) ← $00 − (X + index)

NEG index,Y

Bytes:	3

Cycles:	7

Encoding:	18  60  data

Operation:	(Y + index) ← $00 − (Y + index)


NOP
  back	NOP	No Operation

Description:	This is a single-byte instruction that causes only the program counter to be incremented. No other registers are affected. This instruction is typically used to produce a time delay although some software disciplines discourage CPU frequency-based delays. during debug, NOP instructions are sometimes used to temporarily replace other machine code instructions, thus disabling the replaced instruction(s).

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	1

Cycles:	2

Encoding:	01


ORA
  back	ORA	Inclusive-OR

Operation:	ACCx ← (ACCx) OR (M)

Description:	Performs the logical inclusive-OR between the contents of ACCX and the contents of M and places the result in ACCx. (each bit of ACCX after the operation will be the logical inclusive-OR of the corresponding bits of M and ACCX before the operation).

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

ORA #data

Bytes:	2

Cycles:	2

Encoding:	8A  data

Operation:	ACCA ← ACCA  OR data

ORA data8

Bytes:	2

Cycles:	3

Encoding:	9A  data8

Operation:	ACCA ← ACCA  OR (data8)

ORA data16

Bytes:	3

Cycles:	4

Encoding:	BA  dataHI  dataLO

Operation:	ACCA ← ACCA  OR (data16)

ORA index,X

Bytes:	2

Cycles:	4

Encoding:	AA  index

Operation:	ACCA ← ACCA  OR (X+index)

ORA index,Y

Bytes:	3

Cycles:	5

Encoding:	18  AA  index

Operation:	ACCA ← ACCA  OR (Y+index)

ORAB #data

Bytes:	2

Cycles:	2

Encoding:	CA  data

Operation:	ACCB ← ACCB  OR data

ORAB data8

Bytes:	2

Cycles:	3

Encoding:	DA  data8

Operation:	ACCB ← ACCB  OR (data8)

ORAB data16

Bytes:	3

Cycles:	4

Encoding:	FA  dataHI  dataLO

Operation:	ACCB ← ACCB  OR (data16)

ORAB index,X

Bytes:	2

Cycles:	4

Encoding:	EA  index

Operation:	ACCB ← ACCB  OR (X+index)

ORAB index,Y

Bytes:	3

Cycles:	5

Encoding:	18  EA  index

Operation:	ACCB ← ACCB  OR (Y+index)


PSH
  back	PSH	Push Data onto Stack

Operation:	(SP) ← ACCx

SP ← SP - 1

Description:	The contents of ACCX are stored on the stack at the address contained in the stack pointer. The stack pointer is then decremented.

Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Just before returning from the subroutine, corresponding pull instructions are used to restore the saved CPU registers, so the subroutine will appear not to have affected these registers.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Variations

PSHA

Bytes:	1

Cycles:	3

Encoding:	36

Operation:	(SP) ← ACCA

SP ← SP - 1

PSHB

Bytes:	1

Cycles:	3

Encoding:	37

Operation:	(SP) ← ACCB

SP ← SP - 1


PSHX
  back	PSHX	Push Index Register X onto Stack

Operation:	(SP) ← IXL

SP ← SP - 1

(SP) ← IXH

SP ← SP - 1

Description:	The contents of the index register X are pushed onto the stack (low order first) at the address contained in the stack pointer. The stack pointer is then decremented by two.

Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Just before returning from the subroutine, corresponding pull instructions are used to restore the saved CPU registers, so the subroutine will appear not to have affected these registers.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	1

Cycles:	4

Encoding:	3C


PSHY
  back	PSHY	Push Index Register Y onto Stack

Operation:	(SP) ← IYL

SP ← SP - 1

(SP) ← IYH

SP ← SP - 1

Description:	The contents of the index register Y are pushed onto the stack (low order first) at the address contained in the stack pointer. The stack pointer is then decremented by two.

Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Just before returning from the subroutine, corresponding pull instructions are used to restore the saved CPU registers, so the subroutine will appear not to have affected these registers.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	5

Encoding:	18  3C


PUL
  back	PUL	Pull Data from Stack

Operation:	SP ← SP + 1

ACCx ← (SP)

Description:	The stack pointer is incremented. The ACCX is then loaded from the stack at the address contained in the stack pointer.

Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Just before returning from the subroutine, corresponding pull instructions are used to restore the saved CPU registers, so the subroutine will appear not to have affected these registers.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Variations

PULA

Bytes:	1

Cycles:	4

Encoding:	32

Operation:	SP ← SP + 1

ACCA ← (SP)

PULB

Bytes:	1

Cycles:	4

Encoding:	33

Operation:	SP ← SP + 1

ACCB ← (SP)


PULX
  back	PULX	Pull Index Register X from Stack

Operation:	SP ← SP + 1

IXH ← (SP)

SP ← SP + 1

IXL ← (SP)

Description:	The index register X is pulled from the stack (high order-byte first), beginning at the address contained in the stack pointer plus one. The stack pointer is then incremented by two in total.

Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Just before returning from the subroutine, corresponding pull instructions are used to restore the saved CPU registers, so the subroutine will appear not to have affected these registers.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	1

Cycles:	5

Encoding:	38


PULY
  back	PULY	Pull Index Register Y from Stack

Operation:	SP ← SP + 1

IYH ← (SP)

SP ← SP + 1

IYL ← (SP)

Description:	The index register Y is pulled from the stack (high order-byte first), beginning at the address contained in the stack pointer plus one. The stack pointer is then incremented by two in total.

Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Just before returning from the subroutine, corresponding pull instructions are used to restore the saved CPU registers, so the subroutine will appear not to have affected these registers.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	6

Encoding:	18  38


ROL
  back	ROL	Rotate Left

Operation:

Description:	Shifts all bits of the ACCx or M one place to the left. Bit 0 is loaded from the C bit. The C bit is loaded from the most significant bit of ACCx or M. The rotate operations include the carry bit to allow extension of the shift and rotate operations to multiple bytes. For example, to shift a 24-bit value left one bit, the sequence ASL LOW, ROL MID, ROL HIGH could be used where LOW, MID, and HIGH refer to the low-order, middle, and high-order bytes of the 24-bit value, respectively.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Variations

ROLA

Bytes:	1

Cycles:	2

Encoding:	49

Operation:	Rotate ACCA left

ROLB

Bytes:	1

Cycles:	2

Encoding:	59

Operation:	Rotate ACCB left

ROL data16

Bytes:	3

Cycles:	6

Encoding:	79  dataHI  dataLO

Operation:	Rotate (data) left

ROL index,X

Bytes:	2

Cycles:	6

Encoding:	69  data

Operation:	Rotate (X+index) left

ROL index,Y

Bytes:	3

Cycles:	7

Encoding:	18  69  data

Operation:	Rotate (Y+index) left


ROR
  back	ROR	Rotate Right

Operation:

Description:	Shifts all bits of ACCx or M one place to the right. Bit 7 is loaded with 0. Bit 7 is loaded from the C bit. The C bit is loaded from the least significant bit of ACCx or M. The rotate operations include the carry bit to allow extension of the shift and rotate operations to multiple bytes. For example, to shift a 24-bit value right one bit, the sequence LSR LOW, ROR MID, ROR HIGH could be used where LOW, MID, and HIGH refer to the low-order, middle, and high-order bytes of the 24-bit value, respectively. The first LSR could be replaced by ASR to maintain the original value of the sign bit (MSB of high-order byte) of the 24 bit value.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Variations

RORA

Bytes:	1

Cycles:	2

Encoding:	46

Operation:	Rotate ACCA right

RORB

Bytes:	1

Cycles:	2

Encoding:	56

Operation:	Rotate ACCB right

ROR data16

Bytes:	3

Cycles:	6

Encoding:	76  dataHI  dataLO

Operation:	Rotate (data) right

ROR index,X

Bytes:	2

Cycles:	6

Encoding:	66 data

Operation:	Rotate (X+index) right

ROR index,Y

Bytes:	3

Cycles:	7

Encoding:	18  66  data

Operation:	Rotate (Y+index) right


RTI
  back	RTI	Return from Interrupt

Operation:	SP ← SP + 1	CCR ← (SP)

SP ← SP + 1	ACCA ← (SP)

SP ← SP + 1	ACCB ← (SP)

SP ← SP + 1	IXH ← (SP)

SP ← SP + 1	IXL ← (SP)

SP ← SP + 1	IYH ← (SP)

SP ← SP + 1	IYL ← (SP)

SP ← SP + 1	PCH ← (SP)

SP ← SP + 1	PCL ← (SP)

Description:	The condition code, accumulator B and A, index register X and Y, and the program counter will be restored to a state pulled from the stack. The X bit in the CCR may be cleared as a result of an RTI instruction but may not be set if it was cleared prior to execution of the RTI instruction.

Condition Codes:

S	X	H	I	N	Z	V	C
X	x	X	X	X	X	X	X

Condition code bits take on the value of the corresponding bit of the unstacked CCR except that the X bit may not change from a zero to a one. Software can leave X set, leave X clear, or change X from one to zero. The XIRQ interrupt mask can only become set as a RESET of a reset or recognition of an XIRQ interrupt.

Bytes:	1

Cycles:	12

Encoding:	3B


RTS
  back	RTS	Return from Subroutine

Operation:	SP ← SP + 1	PCH ← (SP)

SP ← SP + 1	PCL ← (SP)

Description:	The stack pointer is incremented by one. The contents of the byte of memory, at the address now contained in the stack pointer, are loaded into the high-order eight bits of the program counter. The stack pointer is incremented by one. The contents of the byte of memory, at the address now contained in the stack pointer, are loaded into the low-order eight bits of the program counter.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	1

Cycles:	5

Encoding:	39


SBA
  back	SBA	Subtract Accumulators

Operation:	ACCA ← ACCA - ACCB

Description:	Subtracts the contents of ACCB from the contents of ACCA and places the result in ACCA. The contents of ACCB are not affected. For subtract instructions, the C bit in the CCR represents a borrow.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Bytes:	1

Cycles:	2

Encoding:	10


SBC
  back	SBC	Subtract with Carry

Operation:	ACCx ← (ACCx) - (M) - C

Description:	Subtracts the contents of M and the contents of C from the contents of ACCX and places the result in ACCX. For subtract instructions the C bit in the CCR represents a borrow.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Variations

SBCA #data

Bytes:	2

Cycles:	2

Encoding:	82  data

Operation:	ACCA ← ACCA - data - C

SBCA data8

Bytes:	2

Cycles:	3

Encoding:	92  data8

Operation:	ACCA ← ACCA - (data8) - C

SBCA data16

Bytes:	3

Cycles:	4

Encoding:	B2  dataHI  dataLO

Operation:	ACCA ← ACCA - (data16) - C

SBCA index,X

Bytes:	2

Cycles:	4

Encoding:	A2  index

Operation:	ACCA ← ACCA - (X+index) - C

SBCA index,Y

Bytes:	3

Cycles:	5

Encoding:	18  A2  index

Operation:	ACCA ← ACCA - (Y+index) - C

SBCB #data

Bytes:	2

Cycles:	2

Encoding:	C2  data

Operation:	ACCB ← ACCB - data - C

SBCB data8

Bytes:	2

Cycles:	3

Encoding:	D2  data8

Operation:	ACCB ← ACCB - (data8) - C

SBCB data16

Bytes:	3

Cycles:	4

Encoding:	F2  dataHI  dataLO

Operation:	ACCB ← ACCB - (data16) - C

SBCB index,X

Bytes:	2

Cycles:	4

Encoding:	E2  index

Operation:	ACCB ← ACCB - (X+index) - C

SBCB index,Y

Bytes:	3

Cycles:	5

Encoding:	18  E2  index

Operation:	ACCB ← ACCB - (Y+index) - C


SEC
  back	SEC	Set Carry

Operation:	C bit ← 1

Description:	Sets the C bit in the CCR.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	1
Bytes:	1

Cycles:	2

Encoding:	0D


SEI
  back	SEI	Set Interrupt Mask

Operation:	I bit ← 1

Description:	Sets the interrupt mask bit in the CCR. When the I bit is set, all maskable interrupts are inhibited, and the MPU will recognize only non-maskable interrupt sources or an SWI.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	1	-	-	-	-
Bytes:	1

Cycles:	2

Encoding:	0F


SEV
  back	SEV	Set Twos Conplement Overflow Bit

Operation:	V bit ← 1

Description:	Sets the twos complement overflow bit in the CCR.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	1	-
Bytes:	1

Cycles:	2

Encoding:	0B


STA
  back	STA	Store Accumulator

Operation:	(M) ← ACCx

Description:	Stores the contents of ACCX in memory. The contents of ACCX remains unchanged.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

STAA data8

Bytes:	2

Cycles:	3

Encoding:	97  data8

Operation:	(data) ← ACCA

STAA data16

Bytes:	3

Cycles:	4

Encoding:	B7  dataHI  dataLO

Operation:	(data16) ← ACCA

STAA index,X

Bytes:	2

Cycles:	4

Encoding:	A7  index

Operation:	(X + Index) ← ACCA

STAA index,Y

Bytes:	3

Cycles:	5

Encoding:	18  A7  index

Operation:	(Y + Index) ← ACCA

STAB data8

Bytes:	2

Cycles:	3

Encoding:	D7  data8

Operation:	(data) ← ACCB

STAB data16

Bytes:	3

Cycles:	4

Encoding:	F7  dataHI  dataLO

Operation:	(data16) ← ACCB

STAB index,X

Bytes:	2

Cycles:	4

Encoding:	E7  index

Operation:	(X + Index) ← ACCB

STAB index,Y

Bytes:	3

Cycles:	5

Encoding:	18  E7  index

Operation:	(Y + Index) ← ACCB


STD
  back	STD	Store Double Accumulator

Operation:	(M) ← ACCA

(M+1) ← ACCB

Description:	Stores the contents of ACCD (ACCA and ACCB) in memory. The contents of ACCD remains unchanged.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

STD data8

Bytes:	2

Cycles:	4

Encoding:	DD  data8

Operation:	(data) ← ACCD

STD data16

Bytes:	3

Cycles:	5

Encoding:	FD  dataHI  dataLO

Operation:	(data16) ← ACCD

STD index,X

Bytes:	2

Cycles:	5

Encoding:	ED  index

Operation:	(X + Index) ← ACCD

STD index,Y

Bytes:	3

Cycles:	6

Encoding:	18  ED  index

Operation:	(Y + Index) ← ACCD


STOP
  back	STOP	Stop Processing

Description:	If the S bit in the CCR is set, the the STOP instruction is disable and operates like the NOP instruction. If the S bit in the CCR is clear, the STOP instruction causes all system clocks to halt, and the system is placed in a minimum-power standby mode. All CPU registers remains unchanged. I/O pins also remain unaffected.

Recovery from STOP may be accomplish by RESET, XIRQ or an unmasked IRQ. When recovering from STOP with XIRQ, if the X bit in the CCR is clear, execution will resume with the stacking operations for the XIRQ interrupt. If the X bit in the CCR is set, masking XIRQ interrupts, execution will resume with the opcode fetch for the instruction which follows the STOP instruction (continue).

An error in some mask sets of the M68HC11 caused incorrect recover from STOP under very specific unusual conditions. If the opcode of the instruction before the STOP instruction came from column 4 or 5 of the opcode map, the STOP instruction was incorrectly interpreted as a two-byte instruction. A simple way to avoid this potential problem is to put a NOP instruction (which is a column 0 opcode) immediately before any STOP instruction.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	1

Cycles:	2

Encoding:	CF


STS
  back	STS	Store Stack Pointer

Operation:	(M) ← SPH

(M+1) ← SPL

Description:	Stores the most significant byte of the stack pointer in memory at the address specified by the program and stores the least significant byte of the stack pointer at the next location in memory, at one plus the addess specified by the program.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

STS data8

Bytes:	2

Cycles:	4

Encoding:	9F  data8

Operation:	(data) ← SP

STS data16

Bytes:	3

Cycles:	5

Encoding:	BF  dataHI  dataLO

Operation:	(data16) ← SP

STS index,X

Bytes:	2

Cycles:	5

Encoding:	AF  index

Operation:	(X + Index) ← SP

STS index,Y

Bytes:	3

Cycles:	6

Encoding:	18  AF  index

Operation:	(Y + Index) ← SP


STX
  back	STX	Store Index Register X

Operation:	(M) ← IXH

(M+1) ← IXL

Description:	Stores the most significant byte of index register X in memory at the address specified by the program and stores the least significant byte of index register X at the next location in memory, at one plus the addess specified by the program.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

STX data8

Bytes:	2

Cycles:	4

Encoding:	DF  data8

Operation:	(data) ← X

STX data16

Bytes:	3

Cycles:	5

Encoding:	FF  dataHI  dataLO

Operation:	(data16) ← X

STX index,X

Bytes:	2

Cycles:	5

Encoding:	EF  index

Operation:	(X + Index) ← X

STX index,Y

Bytes:	3

Cycles:	6

Encoding:	CD  EF  index

Operation:	(Y + Index) ← X


STY
  back	STY	Store Index Register Y

Operation:	(M) ← IYH

(M+1) ← IYL

Description:	Stores the most significant byte of index register Y in memory at the address specified by the program and stores the least significant byte of index register Y at the next location in memory, at one plus the addess specified by the program.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Variations

STY data8

Bytes:	3

Cycles:	5

Encoding:	18  DF  data8

Operation:	(data) ← Y

STY data16

Bytes:	4

Cycles:	6

Encoding:	18  FF  dataHI  dataLO

Operation:	(data16) ← Y

STY index,X

Bytes:	3

Cycles:	6

Encoding:	1A  EF  index

Operation:	(X + Index) ← Y

STY index,Y

Bytes:	3

Cycles:	6

Encoding:	18  EF  index

Operation:	(Y + Index) ← Y


SUB
  back	SUB	Subtract

Operation:	ACCx ← (ACCx) - (M)

Description:	Subtracts the contents of M from the contents of ACCX and places the result in ACCX. For subtract instructions the C bit in the CCR represents a borrow.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Variations

SUBA #data

Bytes:	2

Cycles:	2

Encoding:	80  data

Operation:	ACCA ← ACCA - data

SUBA data8

Bytes:	2

Cycles:	3

Encoding:	90  data8

Operation:	ACCA ← ACCA - (data8)

SUBA data16

Bytes:	3

Cycles:	4

Encoding:	B0  dataHI  dataLO

Operation:	ACCA ← ACCA - (data16)

SUBA index,X

Bytes:	2

Cycles:	4

Encoding:	A0  index

Operation:	ACCA ← ACCA - (X+index)

SUBA index,Y

Bytes:	3

Cycles:	5

Encoding:	18  A0  index

Operation:	ACCA ← ACCA - (Y+index)

SUBB #data

Bytes:	2

Cycles:	2

Encoding:	C0  data

Operation:	ACCB ← ACCB - data

SUBB data8

Bytes:	2

Cycles:	3

Encoding:	D0  data8

Operation:	ACCB ← ACCB - (data8)

SUBB data16

Bytes:	3

Cycles:	4

Encoding:	F0  dataHI  dataLO

Operation:	ACCB ← ACCB - (data16)

SUBB index,X

Bytes:	2

Cycles:	4

Encoding:	E0  index

Operation:	ACCB ← ACCB - (X+index)

SBCB index,Y

Bytes:	3

Cycles:	5

Encoding:	18  E2  index

Operation:	ACCB ← ACCB - (Y+index) - C


SUBD
  back	SUBD	Subtract Double Accumulator

Operation:	ACCD ← (ACCD) - (M:M+1)

Description:	Subtracts the contents of M:M+1 from the contents of double accumulator D and places the result in ACCD. For subtract instructions the C bit in the CCR represents a borrow.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	X	X
Variations

SUBD #data16

Bytes:	3

Cycles:	4

Encoding:	80  dataHI  dataLO

Operation:	ACCD ← ACCD - data16

SUBD data8

Bytes:	2

Cycles:	5

Encoding:	93  data8

Operation:	ACCD ← ACCD - (data8 : data8+1)

SUBD data16

Bytes:	3

Cycles:	6

Encoding:	B3  dataHI  dataLO

Operation:	ACCD ← ACCD - (data16 : data16+1)

SUBD index,X

Bytes:	2

Cycles:	6

Encoding:	A3  index

Operation:	ACCD ← ACCD - (X+index : X+index+1)

SUBD index,Y

Bytes:	3

Cycles:	7

Encoding:	18  A3  index

Operation:	ACCD ← ACCD - (Y+index : Y+index+1)


SWI
  back	SWI	Software Interrupt

Operation:	PC ← PC + 1

(SP) ← PCL	SP ← SP - 1

(SP) ← PCH	SP ← SP - 1

(SP) ← IYL	SP ← SP - 1

(SP) ← IYH	SP ← SP - 1

(SP) ← IXL	SP ← SP - 1

(SP) ← IXH	SP ← SP - 1

(SP) ← ACCA	SP ← SP - 1

(SP) ← ACCB	SP ← SP - 1

(SP) ← CCR	SP ← SP - 1

I ← 1

PC ← SWI vector

Description:	The program counter is incremented by one. The program counter, index registers Y and X, and accumulators A and B are pushed onto the stack. The CCR is then pushed onto the stack. The stack pointer is decremented by one after each byte of data is stored on the stack. The I bit int the CCR is then set. The program counter is loaded with the address stored at the SWI vector, and the instruction execution resumes at this location. This instruction is not maskable by the I bit.

The SWI instruction will not be fetched if any other interrupt is pending. However, once an SWI begins, no other interrupt can be honored until the SWI vector has been fetched.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	1	-	-	-	-
Bytes:	1

Cycles:	14

Encoding:	3F


TAB
  back	TAB	Transfer from Accumulator A to Accumulator B

Operation:	ACCB ← ACCA

Description:	Moves the contents of ACCA to ACCB. The former contents of ACCB are lost; the contents of ACCA are not affected.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Bytes:	1

Cycles:	2

Encoding:	16


TAP
  back	TAP	Transfer from Accumulator A to Condition Code Register

Operation:	CCR ← ACCA

Description:	Transfers the contents of bit position 7-0 of accumulator A to the corresponding bit positions of the CCR. The contents of accumulator A remain unchanged. The X bit in the CCR may be cleared as a result of a TAP instruction but may not be set if it was cleared prior to execution of the TAP instruction.

Condition Codes:

S	X	H	I	N	Z	V	C
X	x	X	X	X	X	X	X

Condition code bits take on the value of the corresponding bit of accumulator A except that the X bit may not change from a zero to a one. software can leave X set, leave X clear or change X from one to zero. The XIRQ interrupt mask can only become set as a result of a RESET or recognition of an XIRQ interrupt.

Bytes:	1

Cycles:	2

Encoding:	06


TBA
  back	TBA	Transfer from Accumulator B to Accumulator A

Operation:	ACCA ← ACCB

Description:	Moves the contents of ACCB to ACCA. The former contents of ACCA are lost; the contents of ACCB are not affected.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	-
Bytes:	1

Cycles:	2

Encoding:	17


TEST
  back	TEST	Test Operation (Test Mode Only)

Description:	This is a single-byte instruction that causes the program counter to be continuously incremented. It can only be executed while in the test mode. The MPU must be reset to exit this instruction. Code execution is suspended during this instruction. This is an illegal opcode when not in test mode.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	1

Cycles:	4 + n

Encoding:	00


TPA
  back	TPA	Transfer from Condition Code Register to Accumulator A

Operation:	ACCA ← CCR

Description:	Transfers the contents of the CCR to corresponding bit positions of the accumulator A. The CCR remains unchanged.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	1

Cycles:	2

Encoding:	07


TST
  back	TST	Test

Operation:	ACCX - $00   or   (M) - $00

Description:	Subtracts 00 from the contents of  ACCX or M and sets the condition codes accordingly.

The subtraction is accomplished internally without modifying either ACCX or M.

The TST instruction provides only minimum information when testing unsigned values. Since no unsigned value is less than zero, BLO and BLS have no utility. While BHI could be used after TST, it provides exactly the same control as BNE, which is preferred. After testing signed values, all signed branches are available.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	X	X	0	0
Variations

TSTA

Bytes:	1

Cycles:	2

Encoding:	4D

Operation:	ACCA - $00

TSTB

Bytes:	1

Cycles:	2

Encoding:	5D

Operation:	ACCB - $00

TST data16

Bytes:	3

Cycles:	6

Encoding:	7D  dataHI  dataLO

Operation:	 (data16) - $00

TST index,X

Bytes:	2

Cycles:	6

Encoding:	6D  index

Operation:	(X + index) - $00

TST index,Y

Bytes:	3

Cycles:	7

Encoding:	18   6D  index

Operation:	(Y + index) - $00


TSX
  back	TSX	Transfer from SP to Index Register X

Operation:	IX ← (SP) + $0001

Description:	Loads the index register X with one plus the contents of the stack pointer. The contents of the stack pointer remain unchanged. After a TSX instruction the index register X points at the last value that was stored on the stack.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	1

Cycles:	3

Encoding:	30


TSY
  back	TSY	Transfer from SP to Index Register Y

Operation:	IY ← (SP) + $0001

Description:	Loads the index register Y with one plus the contents of the stack pointer. The contents of the stack pointer remain unchanged. After a TSY instruction the index register Y points at the last value that was stored on the stack.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	4

Encoding:	18   30


TXS
  back	TXS	Transfer from Index Register X to SP

Operation:	SP ← (IX) - $0001

Description:	Loads the stack pointer with the contents of the index register X minus one. The contents of the index register X remain unchanged.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	1

Cycles:	3

Encoding:	35


TYS
  back	TYS	Transfer from Index Register Y to SP

Operation:	SP ← (IY) - $0001

Description:	Loads the stack pointer with the contents of the index register Y minus one. The contents of the index register Y remain unchanged.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	4

Encoding:	18  35


WAI
  back	WAI	Wait for Interrupt

Operation:	PC ← PC + 1

(SP) ← PCL	SP ← SP - 1

(SP) ← PCH	SP ← SP - 1

(SP) ← IYL	SP ← SP - 1

(SP) ← IYH	SP ← SP - 1

(SP) ← IXL	SP ← SP - 1

(SP) ← IXH	SP ← SP - 1

(SP) ← ACCA	SP ← SP - 1

(SP) ← ACCB	SP ← SP - 1

(SP) ← CCR	SP ← SP - 1

Description:	The program counter is incremented by one. The program counter, index registers Y and X, and accumulators A and B are pushed onto the stack. The CCR is then pushed onto the stack. The stack pointer is decremented by one after each byte of data is stored on the stack.

The MPU then enters a wait state for an integer number of MPU E-Clock cycles. While in the wait state, the address/data bus repeatedly runs read bus cycles to the address where the CCR contents were stacked. The MPU leaves the wait state when it senses any interrupt that has not been masked.

Upon leaving the wait state, the MPU sets the I bit in the CCR, fetches the vector (address) corresponding to the interrupt sensed, and instruction execution is resumed at this location.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-

Although the WAI instruction itself does not alter the condition code bits, the interrupt which causes the MCU to resume porocessing causes the I bit (and the X bit if the interrupt was XIRQ) to be set as the interrupt vector is being fetched.

Bytes:	1

Cycles:	14 + n

Encoding:	3E


XGDX
  back	XGDX	Exchange Double Accumulator and Index Register X

Operation:	IX ←→  ACCD

Description:	Exchanges the contents of double accumulator ACCD and the contents of the index register X. A common use for XGDX is to move an index value into the double accumulator to allow 16-bit arithmetic calculations on the index value before exchanging the updated index value back into the X index register.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	1

Cycles:	3

Encoding:	8F


XGDY
  back	XGDY	Exchange Double Accumulator and Index Register Y

Operation:	IY ←→  ACCD

Description:	Exchanges the contents of double accumulator ACCD and the contents of the index register Y. A common use for XGDY is to move an index value into the double accumulator to allow 16-bit arithmetic calculations on the index value before exchanging the updated index value back into the Y index register.

Condition Codes:

S	X	H	I	N	Z	V	C
-	-	-	-	-	-	-	-
Bytes:	2

Cycles:	4

Encoding:	18   8F


License Agreement
  back End User License Agreement

This License Agreement ("License") permits you to use the enclosed 68HC11 Help files (the "Documentation").

Carefully read the following terms and conditions.  This is a legal agreement between you, the end user, and Virtual Micro Design, concerning the use of this Documentation. This agreement constitutes the complete agreement between you and Virtual Micro Design.  If you do not agree to the terms of the agreement, do not use this documentation and destroy these help files immediatly.

This Documentation may be copied and distributed royalty-free subject to the following conditions:

1. You must copy all Documentation files without modification and must include all pages.

2. You must place all copyright notices and other protective disclaimers and notices contained on the Documentation on all copies of the Documentation.

3. You may not distribute these Documentation help files for profit.

4. You may not use Virtual Micro Design's name, logo, or trademarks to market your software product.

5. You agree to indemnify, hold harmless, and defend Virtual Micro Design and its suppliers from and against any claims or lawsuits, including attorneys' fees, that arise or result from the use or distribution of your software product and any modifications to the Documentation files.

You may distribute copies of this documentation as is without any modification.

Copyright © 1995-1997  Virtual Micro Design. All rights reserved.