Copyright: Copyright ® 1995-1997  Virtual Micro Design


68HC11 Considérations sur la simulation
 Virtual Micro Design  -  68HC11 Help file

License Agreement

Instructions, registers and memory

Instruction Set

Memory Map

Interrupt Sources

Registers

Timer

Pulse Accumulator

Synchronous Serial Interface

Asynchronous Serial Interface

A/D Converter

Virtual Micro Design provides a complete microcontroller simulator for:

- 68HC11, 68HC705, 68HC705B5, 68HC705B16, 68HC705B32,

- PIC16C54, 55, 56, 57, PIC16C554, 556, 558

- PIC16C84, PIC16F84, PIC16C83, PIC16C71

- ST6210, 15, 20, 25,

- ST6252, 53, 60, 62, 63, 65

- 8031,51, 8032,52

Web sites: 	http://idls.izarbel.tm.fr/entp/techer

http://www.sistudio.com/umps

Copyright © 1995-1997 Virtual Micro Design, All rights reserved.


Instruction Set
 68HC11  -  Instruction Set

Alphabetical instruction list

ABA	BRCLR	INX	SBA
ABX	BRN	INY	SBC
ABY	BRSET	JMP	SEC
ADC	BSET	JSR	SEI
ADD	BSR	LDA	SEV
ADDD	BVC	LDD	STA
AND	BVS	LDS	STD
ASL	CBA	LDX	STOP
ASLD	CLC	LDY	STS
ASR	CLI	LSL	STX
BCC	CLR	LSLD	STY
BCLR	CLV	LSR	SUB
BCS	CMP	LSRD	SUBD
BEQ	COM	MUL	SWI
BGE	CPD	NEG	TAB
BGT	CPX	NOP	TAP
BHI	CPY	ORA	TBA
BHS	DAA	PSH	TEST
BIT	DEC	PSHX	TPA
BLE	DES	PSHY	TST
BLO	DEX	PUL	TSX
BLS	DEY	PULX	TSY
BLT	EOR	PULY	TXS
BMI	FDIV	ROL	TYS
BNE	IDIV	ROR	WAI
BPL	INC	RTI	XGDX
BRA	INS	RTS	XGDY


68HC11 Internal Memory Map
 68HC11  - Memory Map

Note: Init Register can remap the RAM area and Register area within 4K-byte block


68HC11 Interrupt Sources
 68HC11  -  Interrupt Sources

Interrupt Source	Vector Address

SCI   (Serial) .............................................	$FFD6 	- $FFD7

SPIE  (Serial) ............................................	$FFD8	- $FFD9

PAII  (Pulse Accumulator) ..........................	$FFDA	- $FFDB

PAOVI  (Pulse Accumulator Overflow) .........	$FFDC	- $FFDD

TOI (Timer Overflow) .................................	$FFDE	- $FFDF

OC5I (Output Compare n°5) .......................	$FFE0	- $FFE1

OC4I (Output Compare n°4) .......................	$FFE2	- $FFE3

OC3I (Output Compare n°3) .......................	$FFE4	- $FFE5

OC2I (Output Compare n°2) .......................	$FFE6	- $FFE7

OC1I (Output Compare n°1) .......................	$FFE8	- $FFE9

IC3I  (Input Compare n°3) ..........................	$FFEA	- $FFEB

IC2I  (Input Compare n°2) ..........................	$FFEC	- $FFED

IC1I  (Input Compare n°1) ..........................	$FFEE	- $FFEF

RTII  (Real Time Counter) ..........................	$FFF0	- $FFF1

IRQ  ( = 0 ) ...............................................	$FFF2	- $FFF3

XIRQ  ( = 0 ) .............................................	$FFF4	- $FFF5

$FFF6	- $FFF7

$FFF8	- $FFF9

COP Watchdog Timeout ............................	$FFFA	- $FFFB

Clock Monitor Fail ......................................	$FFFC	- $FFFD

RESET .....................................................	$FFFE	- $FFFF

I Interrupt Priority resolution

PSEL3	PSEL2	PSEL1	PSEL0	Interrupt Source promoted

0	0	0	0	Timer Overflow

0	0	0	1	Pulse Accumulator Overflow

0	0	1	0	Pulse Accumulator Input Edge

0	0	1	1	SPI Transfer Complete

0	1	0	0	SCI Serial System

0	1	0	1	Reserved (default to IRQ)

0	1	1	0	IRQ (External pin or parallel I/O)

0	1	1	1	Real Time Interrupt

1	0	0	0	Timer Input Capture 1

1	0	0	1	Timer Input Capture 1

1	0	1	0	Timer Input Capture 1

1	0	1	1	Timer Output Compare 1

1	1	0	0	Timer Output Compare 1

1	1	0	1	Timer Output Compare 1

1	1	1	0	Timer Output Compare 1

1	1	1	1	Timer Output Compare 1


68HC11 Registers
 68HC11  -  Registers

General registers

Register Map


68HC11 Timer Section
 68HC11  -  Timer Section

TFLG2 - Timer Flag Register ($X025)

Main Timer Block Diagram


68HC11 Pulse Accumulator
 68HC11  -  Pulse Accumulator

PACTL - Pulse Accumulator Control Register ($X026)

Event Counting Mode  [ PAMOD = 0 ]

Gated-Time Accumulation Mode  [ PAMOD = 1 ]

Pulse Accumulator Block Diagram


68HC11 Synchronous Serial Interface
 68HC11  -  Synchronous Serial Interface

SPCR - SPI Control Register ($X028)


68HC11 Asynchronous Serial Interface
 68HC11  -  Asynchronous Serial Interface

SCCR1 - SCI Control Register 1 ($X02C)

SCCR2 - SCI Control Register 2  ($X02D)

SCSR - SCI Status Register ($X02E)


68HC11 A/D Converter
 68HC11  -  A/D Converter

ADCTL - A/D Control/Status Register ($X030)

ADR1 - A/D Result register 1 ($X031)

ADR2 - A/D Result register 1 ($X032)

ADR3 - A/D Result register 1 ($X033)

ADR4 - A/D Result register 1 ($X034)

*** See also OPTION register which contains the clock selection bit for A/D conversion.


License Agreement
 End user License Agreement

This License Agreement ("License") permits you to use the enclosed 68HC11 Help files (the "Documentation").

Carefully read the following terms and conditions.  This is a legal agreement between you, the end user, and Virtual Micro Design, concerning the use of this Documentation. This agreement constitutes the complete agreement between you and Virtual Micro Design.  If you do not agree to the terms of the agreement, do not use this documentation and destroy these help files immediatly.

This Documentation may be copied and distributed royalty-free subject to the following conditions:

1. You must copy all Documentation files without modification and must include all pages.

2. You must place all copyright notices and other protective disclaimers and notices contained on the Documentation on all copies of the Documentation.

3. You may not distribute these Documentation help files for profit.

4. You may not use Virtual Micro Design's name, logo, or trademarks to market your software product.

5. You agree to indemnify, hold harmless, and defend Virtual Micro Design and its suppliers from and against any claims or lawsuits, including attorneys' fees, that arise or result from the use or distribution of your software product and any modifications to the Documentation files.

You may distribute copies of this documentation as is without any modification.

Copyright © 1995-1997  Virtual Micro Design. All rights reserved.